This invention relates to phase-locked loop (PLL) circuits. More particularly, this invention relates to PLL circuits with reduced lock time.
Generally speaking, PLL circuits generate and output one or more signals locked to both the phase and frequency of an input signal. PLL circuits are widely used in many applications. For example, in one application, PLL circuits are used as multi-phase clock generators that output a plurality of clock signals phase-shifted in equally-spaced increments relative to the input clock signal. PLL multi-phase clock generators are useful in electronic systems having complex timing requirements in which multi-function operations are completed during a single input clock cycle or in which an operation extends over more than one input clock cycle. In another application, PLL circuits are used as frequency multipliers that output a clock signal having a higher frequency than the frequency of the input clock signal.
Conventional PLL circuits have characteristically slow lock times. Lock time is the time required to lock an output signal to both the phase and frequency of an input signal. In particular, conventional PLL circuits must determine both the phase and frequency of an input signal in order to generate a locked output signal. This causes conventional PLL circuits to have increased lock time relative to other clock synchronization circuits (e.g., delay-locked loop (DLL) circuits) that need only determine the phase of the input signal in order to generate a locked output signal. The slow lock times of conventional PLL circuits are also attributable to the inability of conventional PLL circuits to adjust the phase of an output signal without simultaneously adjusting the frequency of the output signal. Nevertheless, PLL circuits have various advantages over other clock synchronization circuits (e.g., PLL circuits generally require smaller delay lines for locking to an input signal than do DLL circuits).
In view of the foregoing, it would be desirable to provide phase-locked loop circuits with reduced lock time.